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Qt Quick Ultralite Automotive Cluster Demo
//============================================================================ // PROJECT = RH850/D1M2H //============================================================================ // C O P Y R I G H T //============================================================================ // Copyright (c) 2017 by RENESAS Electronics (Europe) GmbH. All rights reserved. // Arcadiastrasse 10 // D-40472 Duesseldorf // Germany //============================================================================ //Purpose: RSCFD Hardware Mapping Definition // //Warranty Disclaimer // //Because the Product(s) is licensed free of charge, there is no warranty //of any kind whatsoever and expressly disclaimed and excluded by RENESAS, //either expressed or implied, including but not limited to those for //non-infringement of intellectual property, merchantability and/or //fitness for the particular purpose. //RENESAS shall not have any obligation to maintain, service or provide bug //fixes for the supplied Product(s) and/or the Application. // //Each User is solely responsible for determining the appropriateness of //using the Product(s) and assumes all risks associated with its exercise //of rights under this Agreement, including, but not limited to the risks //and costs of program errors, compliance with applicable laws, damage to //or loss of data, programs or equipment, and unavailability or //interruption of operations. // //Limitation of Liability // //In no event shall RENESAS be liable to the User for any incidental, //consequential, indirect, or punitive damage (including but not limited //to lost profits) regardless of whether such liability is based on breach //of contract, tort, strict liability, breach of warranties, failure of //essential purpose or otherwise and even if advised of the possibility of //such damages. RENESAS shall not be liable for any services or products //provided by third party vendors, developers or consultants identified or //referred to the User by RENESAS in connection with the Product(s) and/or the //Application. // // // //============================================================================ // Environment: Devices: RH850/D1M2H // Assembler: GHS MULTI // C-Compiler: GHS MULTI // Linker: GHS MULTI // Debugger: GHS MULTI //============================================================================ #ifndef _MAP_RSCFD_H #define _MAP_RSCFD_H #include <ports/standardports/standardports.h> /* MAPPED RSCFD: RSCANFD_UCIAPRCN */ #include <map_device.h> #include <rscanfd/rscanfd_uciaprcn/rscfd.h> #ifndef DRIVER_LOCAL #include <rscanfd/rscanfd_uciaprcn/rscfd_p.h> #endif #ifdef APPLICATION_INTERFACE /* optional UART settings */ #endif /* Oscillator frequency in Hertz and floating point */ #define OSCILLATOR_FREQUENCY ( ( float )( 40.0E6 ) ) #define OSC_FREQUENCY ( 40000000 ) /* FURTHER RSCFD OPERATION PROPERTIES */ #define EE_RSCFD_BASE ( 0xFFD00000 ) #define EE_RSCFD_OFFSET_COMMON ( 0x00000000 ) #define EE_RSCFD_OFFSET_AFL ( 0x00001000 ) #define EE_RSCFD_OFFSET_RXMSG ( 0x00002000 ) #define EE_RSCFD_OFFSET_RXFIFO ( 0x00003000 ) #define EE_RSCFD_OFFSET_COMFIFO ( 0x00003400 ) #define EE_RSCFD_OFFSET_TXMSG ( 0x00004000 ) #define EE_RSCFD_OFFSET_TXMMSG ( 0x00004000 ) #define EE_RSCFD_OFFSET_TXHL ( 0x00006000 ) #define EE_RSCFD_OFFSET_RAM ( 0x00006400 ) #define EE_RSCFD_FREQFACTOR ( 1.0 ) #define EE_RSCFD_MAXBAUDRATE ( ( u32 )( OSCILLATOR_FREQUENCY * EE_RSCFD_FREQFACTOR )\ / EE_RSCFD_CLKMINFACTOR ) #define EE_RSCFD_FREQFACTORPLLBP ( 0.2 ) #define EE_RSCFD_MAXBAUDRATEPLLBP ( ( u32 )( OSCILLATOR_FREQUENCY * EE_RSCFD_FREQFACTORPLLBP )\ / EE_RSCFD_CLKMINFACTOR ) #define EE_RSCFD_SHUTDOWNTIMEOUT ( 1000000L ) #define EE_RSCFD_VERBOSE 1 /* PORT DEFINITIONS */ #define EE_RSCFD_PORT_M0RX0 PORT_0 #define EE_RSCFD_PORT_M0TX0 PORT_0 #define EE_RSCFD_PORT_M0RX1 PORT_0 #define EE_RSCFD_PORT_M0TX1 PORT_0 #define EE_RSCFD_PORT_M0RX2 PORT_0 #define EE_RSCFD_PORT_M0TX2 PORT_0 #define EE_RSCFD_PORT_BIT_M0RX0 BIT_5 #define EE_RSCFD_PORT_BIT_M0TX0 BIT_4 #define EE_RSCFD_PORT_BIT_M0RX1 BIT_7 #define EE_RSCFD_PORT_BIT_M0TX1 BIT_6 #define EE_RSCFD_PORT_BIT_M0RX2 BIT_9 #define EE_RSCFD_PORT_BIT_M0TX2 BIT_8 #define EE_RSCFD_PORT_FUNC_M0RX0 PORT_FUNCTION_ALTLV3 #define EE_RSCFD_PORT_FUNC_M0TX0 PORT_FUNCTION_ALTLV3 #define EE_RSCFD_PORT_FUNC_M0RX1 PORT_FUNCTION_ALTLV3 #define EE_RSCFD_PORT_FUNC_M0TX1 PORT_FUNCTION_ALTLV3 #define EE_RSCFD_PORT_FUNC_M0RX2 PORT_FUNCTION_ALTLV3 #define EE_RSCFD_PORT_FUNC_M0TX2 PORT_FUNCTION_ALTLV3 /* INTERRUPT REGISTER MAPPING */ #define EE_RSCFD_INT_BUNDLINGHOOK ( RSCFD_IntBundlingDecode ) // external bundling decoder #define EE_RSCFD_INT_M0GERR ( INTC2EIC69 ) #define EE_RSCFD_INT_M0RXF0 ( INTC2EIC70 ) #define EE_RSCFD_INT_M0RXF1 ( INTC2EIC70 ) #define EE_RSCFD_INT_M0RXF2 ( INTC2EIC70 ) #define EE_RSCFD_INT_M0RXF3 ( INTC2EIC70 ) #define EE_RSCFD_INT_M0RXF4 ( INTC2EIC70 ) #define EE_RSCFD_INT_M0RXF5 ( INTC2EIC70 ) #define EE_RSCFD_INT_M0RXF6 ( INTC2EIC70 ) #define EE_RSCFD_INT_M0RXF7 ( INTC2EIC70 ) #define EE_RSCFD_INT_M0TX0 ( INTC2EIC73 ) #define EE_RSCFD_INT_M0TXA0 ( INTC2EIC73 ) #define EE_RSCFD_INT_M0TXQ0 ( INTC2EIC73 ) #define EE_RSCFD_INT_M0ERR0 ( INTC2EIC71 ) #define EE_RSCFD_INT_M0THL0 ( INTC2EIC73 ) #define EE_RSCFD_INT_M0RXCF0 ( INTC2EIC72 ) #define EE_RSCFD_INT_M0TXCF0 ( INTC2EIC73 ) #define EE_RSCFD_INT_M0TX1 ( INTC2EIC120 ) #define EE_RSCFD_INT_M0TXA1 ( INTC2EIC120 ) #define EE_RSCFD_INT_M0TXQ1 ( INTC2EIC120 ) #define EE_RSCFD_INT_M0ERR1 ( INTC2EIC118 ) #define EE_RSCFD_INT_M0THL1 ( INTC2EIC120 ) #define EE_RSCFD_INT_M0RXCF1 ( INTC2EIC119 ) #define EE_RSCFD_INT_M0TXCF1 ( INTC2EIC120 ) #define EE_RSCFD_INT_M0TX2 ( INTC2EIC182 ) #define EE_RSCFD_INT_M0TXA2 ( INTC2EIC182 ) #define EE_RSCFD_INT_M0TXQ2 ( INTC2EIC182 ) #define EE_RSCFD_INT_M0ERR2 ( INTC2EIC180 ) #define EE_RSCFD_INT_M0THL2 ( INTC2EIC182 ) #define EE_RSCFD_INT_M0RXCF2 ( INTC2EIC181 ) #define EE_RSCFD_INT_M0TXCF2 ( INTC2EIC182 ) #define EE_RSCFD_INTCLEAR ( 0x008F ) // Interrupt mask bit #define EE_RSCFD_INTENABLEDEFAULT ( 0x0040 ) /* The RSCFD Memory Mapping */ #define EE_RSCFD_RAMTEST_PAGES ( 41 ) #define EE_RSCFD_RAMTEST_LASTPGENTRIES ( 160 ) static const u08 ee_rscfd_channels[ EE_RSCFD_MACROS ] = { 3 /* unit 0 */ }; static const u08 ee_rscfd_txqentries[ EE_RSCFD_MACROS ] [ EE_RSCFD_MAXCHANNELS ] [ EE_RSCFD_MAXTXQUEUES ] = { { { ( EE_RSCFD_MAXTXBUFFERS - 1 ) }, { ( EE_RSCFD_MAXTXBUFFERS - 1 ) }, { ( EE_RSCFD_MAXTXBUFFERS - 1 ) }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } }; static struct ee_rscfd_common *ee_rscfd_common_p[ EE_RSCFD_MACROS ] = { ( ee_rscfd_common * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_COMMON + 0x00000000 ) /* unit 0 */ }; static struct ee_rscfd_aflpage *ee_rscfd_aflpage_p[ EE_RSCFD_MACROS ] = { ( ee_rscfd_aflpage * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_AFL + 0x00000000 ) /* unit 0 */ }; static struct ee_rscfd_rxmsg *ee_rscfd_rxmsg_p[ EE_RSCFD_MACROS ] = { ( ee_rscfd_rxmsg * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_RXMSG + 0x00000000 ) /* unit 0 */ }; static struct ee_rscfd_txmsg *ee_rscfd_txmsg_p[ EE_RSCFD_MACROS ] [ EE_RSCFD_MAXCHANNELS ] = { { ( ee_rscfd_txmsg * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_TXMSG + 0x00000000 ), /* unit 0, ch 0 */ ( ee_rscfd_txmsg * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_TXMSG + 0x00000200 ), /* unit 0, ch 1 */ ( ee_rscfd_txmsg * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_TXMSG + 0x00000400 ), /* unit 0, ch 2 */ NULL, NULL, NULL, NULL, NULL } }; static struct ee_rscfd_txmmsg *ee_rscfd_txmmsg_p[ EE_RSCFD_MACROS ] [ EE_RSCFD_MAXCHANNELS ] = { { ( ee_rscfd_txmmsg * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_TXMMSG + 0x00000000 ), /* unit 0, ch 0 */ ( ee_rscfd_txmmsg * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_TXMMSG + 0x00000200 ), /* unit 0, ch 1 */ ( ee_rscfd_txmmsg * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_TXMMSG + 0x00000400 ), /* unit 0, ch 2 */ NULL, NULL, NULL, NULL, NULL } }; static struct ee_rscfd_rxfifo *ee_rscfd_rxfifo_p[ EE_RSCFD_MACROS ] = { ( ee_rscfd_rxfifo * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_RXFIFO + 0x00000000 ) /* unit 0 */ }; static struct ee_rscfd_comfifo *ee_rscfd_comfifo_p[ EE_RSCFD_MACROS ] [ EE_RSCFD_MAXCHANNELS ] = { { ( ee_rscfd_comfifo * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_COMFIFO + 0x00000000 ), /* unit 0, ch 0 */ ( ee_rscfd_comfifo * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_COMFIFO + 0x00000180 ), /* unit 0, ch 1 */ ( ee_rscfd_comfifo * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_COMFIFO + 0x00000300 ), /* unit 0, ch 2 */ NULL, NULL, NULL, NULL, NULL } }; static struct ee_rscfd_thl *ee_rscfd_thl_p[ EE_RSCFD_MACROS ] [ EE_RSCFD_MAXCHANNELS ] = { { ( ee_rscfd_thl * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_TXHL + 0x00000000 ), /* unit 0, ch 0 */ ( ee_rscfd_thl * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_TXHL + 0x00000004 ), /* unit 0, ch 1 */ ( ee_rscfd_thl * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_TXHL + 0x00000008 ), /* unit 0, ch 2 */ NULL, NULL, NULL, NULL, NULL } }; static struct ee_rscfd_ram *ee_rscfd_ram_p[ EE_RSCFD_MACROS ] = { ( ee_rscfd_ram * )( EE_RSCFD_BASE + EE_RSCFD_OFFSET_RAM + 0x00000000 ) /* unit 0 */ }; #endif