/*===============================================================================================

    Copyright (c) 2013 by Renesas Electronics Europe GmbH, a company of the Renesas Electronics
    Corporation. All rights reserved.

  ===============================================================================================

    Warranty Disclaimer

    Because the Product(s) is licensed free of charge, there is no warranty of any kind
    whatsoever and expressly disclaimed and excluded by Renesas, either expressed or implied,
    including but not limited to those for non-infringement of intellectual property,
    merchantability and/or fitness for the particular purpose.
    Renesas shall not have any obligation to maintain, service or provide bug fixes for the
    supplied Product(s) and/or the Application.

    Each User is solely responsible for determining the appropriateness of using the Product(s)
    and assumes all risks associated with its exercise of rights under this Agreement, including,
    but not limited to the risks and costs of program errors, compliance with applicable laws,
    damage to or loss of data, programs or equipment, and unavailability or interruption of
    operations.

    Limitation of Liability

    In no event shall Renesas be liable to the User for any incidental, consequential, indirect,
    or punitive damage (including but not limited to lost profits) regardless of whether such
    liability is based on breach of contract, tort, strict liability, breach of warranties,
    failure of essential purpose or otherwise and even if advised of the possibility of such
    damages. Renesas shall not be liable for any services or products provided by third party
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    connection with the Product(s) and/or the Application.

  ===============================================================================================*/

//============================================================================
// Includes
//============================================================================
#include "lowinit.h"
#include "dr7f701461.dvf.h"
#include "icu_feret.h"
#include "io_macros_v2.h"

#include "lowinit_can.h"

//============================================================================
// Defines
//============================================================================
__IOREG( LOC_APFSGDPROT_INTC2, 0xFFC4C000UL, __READ_WRITE, u32_T);
__IOREG( LOC_APFSGDPROT_PDMA,  0xFFC4C004UL, __READ_WRITE, u32_T);

#ifdef __ghs__
// Force linker to link lowinit obj file.
// This is a compiler "feature".
// See "Forcing the Linker to Pull in a Module From a Library" section from
// a GHS compiler documentation.
void* __ghs_extract_weak___lowinit;
#endif

/*
 * Very early clock tree initialization, directly after
 * _RESET executed.
 */
void __lowinit(void)
{
    /* Prepare MainOSC */
    SYSMOSCC=0x06u;                       /* set MainOSC gain (8 MHz) */
    SYSMOSCST=0x8000u;                    /* set MainOSC stabilization time to 4 ms */
    protected_write(SYSPROTCMD0,SYSPROTS0,SYSMOSCE,0x01u); /* trigger enable (protected write) */
    while (0x4u != (SYSMOSCS&0x04u)){}    /* wait for active MainOSC */

    /* Set PLL0 to 480MHz */
    SYSPLL0C=0x6000003B;   /* PLL0 configuration:
                              Fixed frequency mode(dithering disabled)
                              Nr = 60
                              Pr = 1
                              Mr = 1
                              fPLL= MainOsc * Nr /(Mr * Pr)
                              fPLL=   8Mhz *  60 /( 1 *  1) = 480 MHz */
    protected_write(SYSPROTCMD1,SYSPROTS1,SYSPLL0E,0x01u); /* trigger PLL0 Enable (protected write) */
    while((SYSPLL0S&(1<<2))!=(1<<2)){}   /* wait until PLL0 stable bit is set*/

    /* Set PLL1 to 480MHz */
    SYSPLL1C=0x6000003B;   /* PLL1 configuration:
                              Fixed frequency mode(dithering disabled)
                              Nr = 60
                              Pr = 1
                              Mr = 1
                              fPLL= MainOsc * Nr /(Mr * Pr)
                              fPLL=   8Mhz *  60 /( 1 *  1) = 480 MHz */
    protected_write(SYSPROTCMD1,SYSPROTS1,SYSPLL1E,0x01u);   /* trigger PLL1 Enable (protected write) */
    while((SYSPLL0S&(1<<2))!=(1<<2)){}  /* wait until PLL0 stable bit is set*/

    /* set CPU clock divider to 2 */
    protected_write(SYSPROTCMD1,SYSPROTS1,SYSCKSC_ICPUCLKD_CTL,0x02u); /* divider 2 */
    while(0x02u != SYSCKSC_ICPUCLKD_ACT){}

    /* set CPU clock to PLL1CLK (240MHz)*/
    protected_write(SYSPROTCMD1,SYSPROTS1,SYSCKSC_ICPUCLKS_CTL ,0x04u); /* PLL1CLK */
    while(0x04u != SYSCKSC_ICPUCLKS_ACT){}

    lowinit_can();

    /* Disable the AT guard  */
    LOC_APFSGDPROT_INTC2 = 0x07FFFFFF;
    LOC_APFSGDPROT_PDMA  = 0x07FFFFFF;
}