## I Introduction

The family of Ling adders is a particularly fast adder and is designed using H. Ling’s equations and generally implemented in BiCMOS. It is an upgrade to the already existing Carry-Look-Ahead Adders and is mathematically faster, as it requires lesser steps for the computation of a sum. The circuit of a Ling adder is particularly more complex, and is less favourable for use in VLSI systems due to its complexity and it requires far more extra components than traditional systems. The circuit is divided into 4 parts, which can be denoted by H. Ling’s equations.

## Ii Analysis of Ling’s Equation

### Ii-a Initial Generation of Bits

Ling Adders require to form the bit generate and bit propogate that are used in the regular Carry look ahead adders. It is denoted by the 3 symbols , and .

The generate and propagate bits follow CLA so they can be denoted as,

However, Ling adder requires an extra half bit term which later on simplifies the circuit design, while increasing the overall efficiency of the adder. This half bit generate is denoted by and can be mathematically shown by,

The above mentioned Generate Bit and Propagate Bit are used further to derive the Ling Generates, which are terms that will go on to simplify the final equation. This is particularly important because these generates will form the base of the Ling adder circuit design. These are denoted by and

### Ii-B The CLA Basis of Ling’s Equations

The CLA depends upon the carry out term of the previous for the new carry terms.

which is similar to the Simple Ripple Adder which uses the carry output of the preceding data bits for forward addition.

Similarly based on the above concept, Ling created a new theoretical carry generate which he denoted by H. This is used later on in the Adder to generate the sum . The term H is given by,

where,

Introduction of ling carry is one of the major reasons why Ling Adder is a fast yet complex adder. Use of Ling carry equations decreases the number of boolean terms during its operations, but increases the design complexity.

### Ii-C Ling Generate and Propagate

Ling proposed the use of Ling Propagate and Ling Generate to simplify the operations of the Ling adder. It is very important, as this is the first step where we can see how the terms are generated by using the and terms. These terms can be derived by

and

Ling generate and propagate terms are used to calculate the Ling carry term . Later on in the Adder design, the sum terms are directly influenced by the all the Ling terms.

### Ii-D Ling Sum Term

The final sum term for the pair terms of a and b are devised by following Ling sum equations, which take in lesser number of inputs, and hence decrease the lag in the system.

If we assume that all input gates have only two inputs, we can see that calculation of CLA carry requires 5 logic levels, whereas that for ling carry requires only four. Although the computation of carry is simplified, calculation of the sum bits using Ling carries is much more complicated. The sum bit, when calculated by using traditional carry, is given to be,

We note that we require to use both the carry output and half-bit term from the first operation block.

Using the above term in the Ling Sum Equation,

on break down,

Hence, the output value for is given by and .

## Iii Ling Carry Equation

### Iii-a General expansion and Substitution

Earlier in the CLA basis subsection of Ling Equation analysis, we came across 2 equations,

and,

Since we know that,

Thus we can write the Carry Output as,

But we know that,

Thus we can simplify the equations to Ling generate-propagate terms.

### Iii-B Application in 4-Bit System

In a 4-bit adder design, we require the terms , , and .

From the Ling generate-propagate equations and the expanded Ling Carry equation in the previous subsection, we can write the 4 terms as,

It is noted that the complexity of the system will increase with increase of Input terms.

## Iv Logic design of 4-Bit Ling Adder

From all the above sections and designs, we can design the 4 bit Ling Adder.

As per the design, The flowing outputs are passed through basic OR and AND gates to satisfy equations.The carry is safely calculated as

Similarly, each block present in the Logic Diagram represents an operation step described in each subsection of the logic analysis.

The use of free gates in the circuit represent the operations used to calculate . The initial and dont exist during the case and hence they are taken as logical or value by grounding them.

Effectively, the overall circuit follows the final equation

and generates a carry term in-case the overall sum exceeds the 4-bit output range.

## V PCB and CAD Design

The system can be designed in real time by the use of actual logic gate ICs belonging to the 74xx family. These ICs usually consist of 16 (DIL16) or 14 (DIL14) pins, and require low power. From the above Logisim design of the Ling Adder, we can start designing the same circuit on any EDA or CAD software. Due to its high complexity, the circuit has to be designed on the both sides of a pcb and uses multiple vias for the on-board connections.

## Vi Conclusion

Hence, a basic 4-Bit Ling adder circuit was designed according to Huey Ling’s equations. In 4-Bit arithmetic system, the CLA requires 5 terms, whereas the Ling adder requires a maximum input of 4 terms, thereby decreasing the time required for computation. When this adder is cascaded for higher number of Bit input terms, the CLA will come across an increase in operation times. But in a ling adder, this time increase would be much lesser than the other binary adders.

## Acknowledgment

The authors would like to thank Mr. AVM Manikandan (Asst. Professor, ECE Dept.) for his teachings, his support and guidance, under which the project was successfully completed.

## References

- [1] H. Ling, ”High Speed Binary Parallel Adder”, IEEE Transactions on Electronic Computers, EC-15, p. 799-809, October, 1966
- [2] G. Dimitrakopoulos ,D. Nikolos, ”High-speed parallel-prefix VLSI Ling adders”, IEEE Transactions on Computers, January, 2005
- [3] Deepa Yagain, Vijaya Krishna A, and Akansha Baliga, “Design of High-Speed Adders for Efficient Digital Design Blocks,” ISRN Electronics, vol. 2012, Article ID 253742, 9 pages, 2012. doi:10.5402/2012/253742
- [4] N. T. Quach, M. J. Flynn, ”High-Speed Addition in CMOS”, IEEE Transactions on Computers, Vol.41, No.12, December, 1992.

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